The present invention relates to a semiconductor device having current-constricting spaces and a method of manufacturing the semiconductor device, and more particularly to an improved, buried-heterostructure (BH) type semiconductor laser having a self-aligned constricted mesa.
Conventional InGaAsP/InP-based, BH-type semiconductor lasers and methods of manufacturing the lasers will be described below.
First, a method of manufacturing an InGaAsP BH laser, in which MOVPE (Metal Organic Vapor Phase Epitaxial) crystal growth method is utilized, will be explained with reference to FIGS. 10A to 10D.
First, as shown in FIG. 10A, an n-type InP buffer layer 2, an undoped InGaAsP active layer 3, and a p-type InP cladding layer 4 are successively grown by MOVPE growth method, on a (100) n-type InP substrate 1. A double heterostructure composed of the n-type InGaAsP layer 3 and p-type InP layer 4 is thereby formed. Next, as shown in FIG. 10B, an SiO.sub.2 film 10 is deposited by CVD (Chemical Vapor Deposition) method on the p-type InP layer 4 and patterned, forming a stripe. Using the stripe of the SiO.sub.2 film 10 as a mask, the p-type InP layer 4, undoped InGaAsP active layer 3 and n-type InP buffer layer 2 are etched, thereby forming a mesa stripe. Thus, the active layer 3 becomes a stripe.
As shown in FIG. 10C, a p-type InP burying layer 5 is formed by MOCVD method on the n-type InP buffer layer 2, on either side of the stripe-shaped active layer 3. Further, a p-type InP burying layer 6 is then formed by MOCVD method on the burying layer 5, on either side of the active layer 3.
Finally, as shown in FIG. 10D, the SiO.sub.2 is removed, a p-type InP layer 7 is grown on all exposed layers, and a p.sup.+ -type InGaAsP ohmic contact layer 8 is grown on the p-type InP layer. As a result, an InGaAsP BH laser is manufactured.
To oscillate the laser (i.e. to emit a laser beam), the substrate 1 is connected to the ground and a positive voltage is applied to the ohmic contact layer 8. An electric current is thereby supplied to the layer 8. The current is blocked by the reverse bias junction formed at the interface between the burying layers 5 and 6. This is first-step current constriction. Residual currents leaking out of the first-step constriction mechanism are blocked by the InP forward junction constituted by the p-type InP burying layer 5 and the n-type InP buffer layer 2 as second-step of constriction. As a result, the current flows or concentrate focus onto the InGaAsP active layer 3. The second-step constriction is explained as follows. That is, since the built-in potential of an InGaAsP layer is lower than that of an InP layer, the current more easily flows at the InGaAsP forward junction than at the InP forward junction. The current is therefore constricted.
However, the current cannot be efficiently constricted when a high voltage is applied between the electrodes to obtain larger output power. This is because the difference between the built-in potentials of the InGaAsP and InP layers is not sufficient under highly-biased condition.
The p-type InP layer 7, the n-type InP burying layer 6, p-type InP burying layer 5 and n-type InP buffer layer 2 constitute a pnpn thyristor. The thyristor may turn on when a leakage current flowing from the InP burying layer 5 to the InP buffer layer 2 and acts as the gate current of the thyristor. In this case, the leakage current inevitably increases rapidly.
The parasitic capacitance C of the reverse bias junction between the p-type InP burying layer 5 and the n-type InP burying layer 6 limits the response frequency of the semiconductor laser. The laser can hardly be used in optical communication system at a rate of 10 Gbps or more. To reduce the parasitic capacitance C, the area of the reverse bias junction between the buried layers 5 and 6 must be reduced.
The leakage current characteristic of the buried-heterostructure laser shown in FIG. 10D depends on the thickness, carrier concentrations, shapes and the like of the p-type InP burying layer 5 and the n-type InP burying layer 6, both provided near the active layer 3. Hence, semiconductor lasers of this type may greatly differ in their characteristics.
Now, a method of manufacturing a semiconductor laser having an InGaAsP/InP self-aligned constricted mesa will be explained with reference to FIGS. 11A to 11E. The method is disclosed in, for example, U.S. Pat. No. 4,870,469, U.S. Pat. No. 4,958,202, and Y. Hirayama et al., "High-speed 1.5 .mu.m self-aligned constricted mesa DFB lasers grown entirely by MOCVD," IEEE Journal of Quantum Electronics, Vol. 25, pp. 1320-1323, 1989.
First, as shown in FIG. 11A, an n-type InP buffer layer 12, an undoped InGaAsP active layer 13, a p-type InP cladding layer 14 are successively grown on a (100) n-type InP substrate 11. A double heterostructure is thereby formed.
As shown in FIG. 11B, a resist (not shown) is coated on the InP cladding layer 14 and patterned so as to remove two elongated parts (having a width of 1 .mu.m) of the active layer 13 in order to obtain a stripe-shaped active layer. Using the patterned resist as a mask, the p-type InP cladding layer 14, undoped InGaAsP active layer 13 and n-type InP buffer layer 12 are etched one after another. Two grooves 15 are thereby formed in these layers 12, 13 and 14, exposing two parts of the n-type InP substrate 11.
Then, as shown in FIG. 11C, a p-type InP layer 17 is formed on the exposed parts of the substrate 11 and also on the p-type InP layer 14. Further, a p.sup.+ -type InGaAsP ohmic contact layer 18 is grown on the p-type InP layer 17.
Thereafter, a resist (not shown) is coated on the ohmic contact layer 18 and patterned by means of photolithography so as to form two grooves in the layers 18, 17 and 14. Using the patterned resist as a mask, the InGaAsP layer 18 is etched to have two slits later. Using the layer 18 thus etched, as a mask, the p-type InP layers 17 and 14 are etched with HCl. Two grooves 19 are thereby formed in the layers 14, 17 and 18. Since HCl is a selective etchant, only the p-type InP layers 17 and 14 are etched, and the undoped InGaAsP active layer 13 is not etched at all. In other words, the etching automatically stops at the active layer 13. As a result, the structure shown in FIG. 11D is obtained. As seen from FIG. 11D, the structure has a mesa 20 which includes the stripe-shaped active layer and which is sufficiently broad, covering both grooves 15 made in the layers 12, 13 and 14.
Then, those parts of the undoped InGaAsP active layer 13 which are left outside the grooves 15 are etched away with a H.sub.2 SO.sub.4 -based etchant, which is a selective etchant which reacts with InGaAsP only, not with InP. The InP filling the grooves 15 function as etching stoppers, automatically stopping the etching. As a result, spaces 21 are formed outside the grooves 15 as illustrated in FIG. 11E. Finally, an insulating film (not shown) is deposited on the resultant structure and electrodes (not shown) are formed. Thus manufactured is a semiconductor laser having an InGaAsP/InP self-aligned constricted mesa is manufactured.
In this semiconductor laser, a leakage current flows in only the InP forward junction 22 just beside the stripe-shaped active layer 13 and having a small junction area.
A semi-insulating crystal layer may be grown, surrounding the mesa section of a semiconductor layer, as will be explained with reference to FIGS. 12A to 12C.
First, as shown in FIG. 12A, a semi-insulating InP burying layer 95 doped with Fe is grown by means of MOVPE crystal growth method on, for example, n-type InP substrate 90. The semi-insulating InP layer has a high resistance. If a p-type InP layer 97 doped with Zn is formed on the semi-insulating InP burying layer 95 as shown in FIG. 12B, mutual diffusion of Zn and Fe will take place and the InP burying layer 95 will no longer be semi-insulating. To prevent this, a thin n-type InP 96 is grown on the semi-insulating InP burying layer 95 as is illustrated in FIG. 12C. Finally, the p-type InP layer 97 is grown on the n-type InP layer 96.
In practice, a semi-insulating crystal layer is not grown on the entire surface of the substrate 90. Usually, a layer having an pn-junction is processed into a mesa-shaped layer, and a semi-insulating layer is formed, surrounding the mesa-shaped junction. The pn-junction performs the main function of the semiconductor device. On the other hand, the semi-insulating layer achieves electric isolation, reduces parasitic capacitance, constricts the current at the pn-junction, and makes flat the upper surface of the device.
A semiconductor device comprising a mesa section which has an pn-junction and a semi-insulating layer surrounding the mesa section is known. How this device is manufactured will be explained, with reference to FIGS. 13A to 13D.
At first, an n-type InP layer 91, an undoped InGaAsP active layer 92, a p-type InP layer 93 and a p.sup.+ -type InGaAsP ohmic contact layer 94 are successively grown on a (100) n-type InP substrate 90. Then, these layers 91 to 94 are etched, forming a mesa structure, as illustrated in FIG. 13A. This is a double heterostructure like the InGaAsP/InP self-aligned constricted mesa of the semiconductor laser shown in FIG. 10D.
Next, a semi-insulating InP burying layer 95 is formed on the substrate 90, covering the sides of the InGaAsP active layer 92, and an n-type InP layer 96 is formed on the semi-insulating InP burying layer 95.
If the semi-insulating InP burying layer 95 is thick, covering the sides of the n-type InP layer 91, undoped InGaAsP active layer 92 and p-type InP layer 93 as is shown in FIG. 13B, mutual diffusion will take place between the semi-insulating InP layer buried 95 and the p-type InP layer 93 and the InP burying layer 95 will no longer semi-insulating.
If the semi-insulating InP burying layer 95 is thin, just covering the sides of the n-type InP layer 91 but not the sides of the InGaAsP active layer 92, as is illustrated in FIG. 13C, the n-type InP layer 96 will contact the n-type InP buffer layer 91. In this case, an interface 98 is formed between two n-type layers 91 and 96. A current is likely to flow via this interface 98, bypassing the InGaAsP active layer 92. That is, the current cannot be constricted in the InGaAsP active layer 92. Further, a high voltage is likely to be applied to the pn-junction 99 between the n-type InP layer 96 and the p-type InP layer 93, because the interface 99 is located above the InGaAsP active layer 92. Consequently, the pn-junction becomes electrically conductive, thus forming a current bypass, after the semiconductor device oscillate. Since the vertical pn-junction 99 has a different facet orientation, from the epitaxial orientation the junction 99 will likely have defects, causing a current to leak through it.
To solve these problems, the semi-insulating InP burying layer 95 may deposited on the substrate 90 to such a thickness that its upper surface is flush with that of the InGaAsP active layer 92, thus completely covering the sides of the n-type InP buffer layer 91 and active layer 92, as is illustrated in FIG. 13D. In practice, however, it is very difficult to control the thickness of the semi-insulating InP burying layer 95 so precisely. Could it be controlled so, the pn-junction 99 is still likely to have defects, and a current may leak through the pn-junction 99.
Thus, it is impossible to constrict a current effectively in any semiconductor device wherein a pn-junction is covered with a semi-insulating crystal layer. From this viewpoint, the aforementioned self-aligned constricted mesa is more advantageous than a mesa surrounded by a semi-insulating crystal layer. The self-aligned constricted mesa has a very small capacitance because it has small junction area and has no reverse junction. It should therefore be used in a high-speed semiconductor device.
There is two problems with the self-aligned constricted mesa, however. First, the leakage current increases when a high voltage is applied to the forward junction. Second, the mesa is mechanically weak because a stress concentrates on the bottle-necked constricted section.
In a constricted mesa structure, connection between the electrode provided on the stripe-shaped mesa having a mushroom-shaped cross section and the bonding pads provided on the upper surfaces of the other mesa. The electrode on the mesa is spaced apart from the bonding pads by grooves. Here arises a problem. Metalization for electrical connection must be carried out be using a step-recoverage method or air-bridge method.